1. Field of the Invention
This invention relates to integrated circuits and, in particular, to die level electrical testing and burn-in of a semiconductor die on which electrically conductive circuitry is formed.
2. Related Art
FIG. 1 is a flow chart of a standard method for producing packaged integrated circuits. Wafer fabrication 110, wafer sort 120, and die separation and preparation 130 produce individual integrated circuit chips (semiconductor dice on which integrated circuitry is formed). Each individual chip is then enclosed in a protective covering during assembly into an integrated circuit package 140. During post-packaging integrated circuit testing 150, the packaged integrated circuit chips are subjected to electrical testing and burn-in to verify acceptable operation of the integrated circuit chips.
Since not all integrated circuit chips prove to operate acceptably after being packaged, a certain number of packaged integrated circuits must be either reworked (i.e., bad chips replaced with new chips that are then electrically tested and burned in) before use or discarded. This unreliability of chip operation adds to the expense of producing packaged integrated circuits. The additional cost is even greater for high cost or high complexity packaged integrated circuits such as hybrid circuits, chip-on-board, or multichip modules.
The electronics industry continually demands components with faster response times than existing components. Multichip integrated circuits (i.e., a plurality of integrated circuit chips formed in a single package) are increasingly desirable as a means to meet this need for faster performance since the chips can be located closer together in the package than is possible when each chip is packaged in a separate package. The single biggest obstacle to increased use of multichip integrated circuits is the high level of failure of packaged multichip integrated circuits, relative to single chip integrated circuits, during the testing and burn-in phase of production.
The high percentage of multichip integrated circuits that fail during post-packaging testing is a statistical consequence of the combination in one package of a relatively large number of chips characterized by a chip yield significantly below 100%. Here, chip yield is defined as the probability that any given chip will operate acceptably during post-packaging integrated circuit testing 150. For instance, assuming a chip yield of 95%, the probability that an eight chip package will operate acceptably during post-packaging integrated circuit testing 150 is 66%. In practice, a chip yield of 95% is high. For the more common situation in which the chip yield is lower than 95%, the acceptability rate of the eight chip package rapidly decreases. Further, as the number of chips in a package increases, the acceptability rate also rapidly decreases.
The high failure level of packaged multichip integrated circuits makes production of packaged multichip integrated circuits expensive. In order to avoid discarding packaged multichip integrated circuits that fail post-packaging testing, redundant sets of bond pads are built on the substrate of the multichip integrated circuit for each chip location. If bad chips are identified during the testing of the packaged multichip integrated circuit, the bad chips are removed and replaced with new chips which are attached to an unused set of bond pads. The process is repeated until the packaged multichip integrated circuit performs acceptably.
This process requires re-opening the package to replace the bad chip or chips, re-sealing the package, and retesting the packaged multichip integrated circuit with the new chip or chips, thus increasing the time and cost of producing a packaged multichip integrated circuit. This process also necessitates that the package be made slightly larger than would otherwise be necessary to accommodate the additional sets of bond pads needed to accommodate any required new chips. Further, in order to know which chip or chips of a packaged multichip integrated circuit has failed, the multichip integrated circuit may allow testing the operation of individual chips, increasing the complexity (and thus cost) of the multichip integrated circuit design. Alternatively, if individual chips can not be tested, then, when failure of a chip in a packaged multichip integrated circuit occurs, each chip of the packaged multichip integrated circuit must be replaced, one at a time, and the packaged multichip integrated circuit retested until the failed chip is located. It would be expected that identification of a bad chip in this way would typically take several iterations of chip replacement and retesting, making production of a packaged multichip integrated circuit correspondingly more expensive. If more than one chip is bad, even more reworking of the packaged multichip integrated circuit is required. Finally, the retesting that is necessary when a bad chip must be replaced uses up some of the useful life of the good chips within the package, thus shortening the life of the multichip integrated circuit.
In an attempt to increase the reliability of integrated circuit chips before they are committed to a production integrated circuit package, methods have been developed to perform a wafer level electrical test and burn-in. However, these methods are extremely complex and, in any case, they are only partial solutions to the problem of producing more reliable chips since there are limits on how severely the chips can be stressed, how well they can be clocked and whether they can be characterized for speed at the wafer level.
Tape automated bonding (TAB) allows chips to be electrically tested and burned in prior to being committed to a particular package; however, TAB is expensive and may only be used for a limited number of package types. Further, TAB requires more space for the chips in the package. Additionally, since the chips are typically left on the TAB tape after testing, the outer lead bond must be broken if the chips are to be used in a package other than the one in which they were tested. Breaking of the outer lead bond is difficult to do, making use of TAB as a testing and burn-in method troublesome.
A chip carrier has also been used to electrically test and burn in integrated circuit chips. The die is mounted in the cavity of a chip carrier and covered with a lid. Conductive traces are formed on the interior surface of the lid. The lid is aligned with the die and pressure applied to the lid such that one end of each of the traces contacts a bond pad on the die. The other end of each of the traces is used to make connection to test circuitry outside the chip carrier. While the lid is held pressed against the die, the die is electrically tested and burned in. After test and burn-in, the die is removed from the carrier and, if the die performed acceptably during test and burn-in, the die is used in a production integrated circuit package or shipped as a tested good die.
This method requires a specially designed carrier and lid for each type of integrated circuit chip so that for each type of chip tested, a new lid and possibly carrier must be used. Consequently, the method is expensive, particularly when used for testing small lots of chips.
Existing methods of testing and burning in integrated circuit chips at the die level provide only partial test and burn-in or require complex and/or expensive techniques. Thus, there is a need for a simple and inexpensive method of fully testing and burning in integrated circuit chips at the die level.